Update: 29 September, 2023
The DS90C363/DS90CF364 is a +3.3V programmable LVDS transmitter and receiver suitable for 18-bit flat panel display (FPD) link with a frequency support of 65 MHz. The transmitter converts 21 bits of CMOS/TTL data into three LVDS data streams and transmits a phase-locked transmit clock over a fourth LVDS link. The receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. With a 65 MHz clock, the data throughput is 170 MB/s. The transmitter features programmable edge data strobes for easy interface with various graphics controllers. The transmitter can be programmed for rising edge strobe or falling edge strobe through a dedicated pin. A rising edge transmitter can interoperate with a falling edge receiver (DS90CF364) without any translation logic. This chipset is an ideal solution to address EMI and cable size issues associated with wide, high-speed TTL interfaces.
File format: PDF
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MD5 Checksum: 7F6347EC2BC1849868FD187602AC9BBE
Publication date: 03 May, 2012
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PDF Link: NATIONAL SEMICONDUCTOR DS90C363/DS90CF364 Manual PDF