Update: 30 September, 2023
This product is a low phase noise, phase-locked loop (PLL) 6-output clock generator with integrated 2.5 GHz VCO. It has 1 differential or 2 single-ended reference inputs, and can accept LVPECL, LVDS or CMOS reference signals, up to 250 MHz. Digital or analog lock detect can be selected. It has 3 pairs of 1.6 GHz LVPECL outputs. Each output pair shares a 1:32 divider with coarse phase delay. Additive output jitter is 225 fs rms. Channel-to-channel skew paired outputs are less than 10 ps. All outputs are automatically synchronized on power-up. Manual output synchronization is available. This product is suitable for low jitter, low phase noise clock distributors, digital baseband and wireless communication systems.
File format: PDF
Size: -
MD5 Checksum: 4F128583DE4494327C4AD89DFD894659
Publication date: 03 May, 2012
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PDF Link: ANALOG DEVICES AD9518-1 English products handbook PDF