Update: 30 September, 2023
The AD9517-1 is a 12-output clock generator with an integrated 2.5 GHz VCO. The clock generator features a low phase noise, phase-locked loop (PLL). The AD9517-1 supports 1 differential or 2 single-ended reference inputs and has reference monitoring capability. In addition, the clock generator supports automatic revertive and manual reference switchover/holdover modes and accepts LVPECL, LVDS or CMOS references to 250 MHz. The AD9517-1 has a programmable delay path to the PFD and supports digital or analog lock detect. The clock generator has 2 pairs of 1.6 GHz LVPECL outputs, each output pair shares a 1:32 divider with coarse phase delay. Additive output jitter is 225 fs rms, channel-to-channel skew paired outputs are <10 ps. The AD9517-1 also has 2 pairs of 800 MHz LVDS clock outputs, each output pair shares two cascaded 1:32 dividers with coarse phase delay. Additive output jitter is 275 fs rms, fine delay adjust (Δt) is supported on each LVDS clock output.
File format: PDF
Size: -
MD5 Checksum: 98788616D16B787A3B0C312A78431367
Publication date: 03 May, 2012
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PDF Link: ANALOG DEVICES AD9517-1 handbook (1) PDF