Update: 30 September, 2023
AD9522-5 is a low phase noise, phase-locked loop (PLL) from Analog Devices. This chip supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz, supports 1 differential or 2 single-ended reference inputs, accepts CMOS, LVPECL or LVDS references to 250 MHz, accepts 16.62 MHz to 33.33 MHz crystal as reference input, has an optional reference clock doubler, supports reference monitoring capability, has auto and manual reference switchover/holdover modes with selectable revertive/nonrevertive switching, glitch-free switchover between references, automatic recovery from holdover, supports digital or analog lock detect, optional zero delay operation. This chip has 12 800 MHz LVDS outputs, divided into 4 groups, each group of 3 has a 1-to-32 divider with phase delay. The additive broadband jitter is as low as 242 fs rms, grouped outputs channel-to-channel skew < 60 ps, each LVDS output can be configured as an independent output or connected to the PLL's internal 1-to-32 divider.
File format: PDF
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MD5 Checksum: 57218896031F21F1996940DFEEE6C065
Publication date: 24 March, 2012
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PDF Link: ANALOG DEVICES AD9522-5 handbook PDF