Pericom Manuals

The PI6C2404A-1 is a PLL-based, zero-delay buffer, with the ability to distribute four outputs of up to 133 MHz at 3.3V. Two banks of two outputs exist, OUTA[1–2] and OUTB[1–2]. An external feedback pin is used to synchronize the outputs to the input; the relationship between loading of this signal and the other outputs determines the input-output delay. The PI6C2404A-1 is characterized for both commercial and industrial operation.

PI6C2310 is a low skew, low jitter, PLL clock buffer with divider or multiplier designed for PCI-X application in servers and worksta- tions. There are two selectable input ranges using HF# input: 10-40 MHz and 40-80 MHz. All outputs are synchronized to the input and to the other outputs. Each output can be independently turned off to reduce EMI and power consumption.

The document describes the features and characteristics of a product.

The PI6C2305-1 is a 3.3V zero-delay buffer designed to distribute clock signals in applications including PC, workstation, datacom, telecom, and high-performance systems. The device provides 5 copies of clocks that have less than 350ps propagation delay compared to a reference clock. The skew among the output clock signals for PI6C2305-1 is less than 250ps. When there are no rising edges on the REF input, the PI6C2305-1 enters a power-down state. In this mode, the PLL is off and all outputs are three-stated. This results in less than 50µA of current draw. The PI6C2305-1H is the high-drive version of the PI6C2305-1, featuring faster rise and fall times.

The document is an introduction to a product, including its connection methods, power requirements, and functional features.

PI6C20800S is a PCI Express, high-speed, low-noise differential clock buffer designed to be a companion to PI6C410BS PCI Express clock generator for Intel server chipsets. The device distributes the differential SRC clock from PI6C410BS to eight differential pairs of clock outputs either with or without PLL. The input SRC clock can be divided by 2 when SRC_DIV# is LOW. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated. When PWRDWN# is LOW, the SDA and SCLK inputs must be Tristated.

PI6C18551 is a low skew, low noise and high-speed clock buffer for computing, networking and communication applications. It is a non-inverting buffer with four outputs from a single input. The outputs are controlled by output enable pin (OE), outputs are tri-states when OE is LOW, and outputs are enabled when OE is HIGH.

This datasheet provides detailed pin definition information for the PS8469 chip

PS8466 is a DDR2 SDRAM controller

The PI6C185-01 is a high-speed low-noise 1-5 non-inverting buffer designed for SDRAM clock buffer applications. This buffer is intended to be used with the PI6C10X clock generator for Intel Architecture-based Mobile systems.

This document is a specification for a product, including the product's brand, model, and feature information

The PI6C184 is a high-speed, low-noise, non-inverting 1-13 buffer designed for SDRAM clock buffer applications. This buffer is intended to be used with the PI6C104 clock generator for Intel Architecture for both desktop and mobile systems. At power-up, all SDRAM outputs are enabled and active. The I2C Serial control may be used to individually activate/deactivate any of the 13 output drivers. Note: Purchase of I2C components from Pericom conveys a license to use them in an I2C system as defined by Philips®.

This document is the datasheet for a certain product

PI6C180 is a high-speed low-noise 1-18 non-inverting buffer designed for SDRAM clock buffer applications. It operates at a frequency of up to 125 MHz and has low noise and low skew characteristics. The product features an I2C serial configuration interface and supports up to four SDRAM DIMMs. It also has multiple VDD and VSS pins for noise reduction. The product operates on a 3.3V power supply voltage and has a separate Hi-Z pin for testing. It is packaged in a 48-pin SSOP package.

This document describes the features and characteristics of a product named PS8141D. The product is a high-speed low-noise non-inverting 1-18 buffer designed for SDRAM clock buffer applications. It supports up to four SDRAM DIMMs and has low skew (< 250ps) between any two output clocks. The product features an I2C Serial Configuration interface, multiple VDD and VSS pins for noise reduction, and operates at a 3.3V power supply voltage. It also has a separate Hi-Z pin for testing. The product is available in a 48-pin SSOP package.