NXP manuals, page 18
NXP 74HC_HCT2G126 buffer
The 74HC2G126; 74HCT2G126 is a dual buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
NXP 74HC_HCT3G07 buffer
The 74HC3G07; 74HCT3G07 is a triple buffer with open-drain outputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
NXP 74HC_HCT3G34 buffer
The 74HC3G34; 74HCT3G34 is a triple buffer. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
NXP 74HC_HCT3G14 Trigger
The 74HC3G14; 74HCT3G14 is a triple inverter with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals.
NXP 74HC_HCT40105 Register
The 74HC40105; 74HCT40105 is a first-in/first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It can handle input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in that position. The control flip-flop d
NXP 74HC_HCT2G32 Dual 2-input OR gate
The 74HC2G32; 74HCT2G32 is a dual 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
NXP 74AXP1G08 2-input AND gate
The 74AXP1G08 is a single 2-input AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.7 V to 2.75 V. It is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
NXP 74AXP1G125 buffer
The 74AXP1G125 is a single buffer/line driver with 3-state output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.7 V to 2.75 V. It is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
NXP 74F126 buffer
The 74F126 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a high-impedance OFF-state.
NXP 74F38 buffer
The 74F38 provides four 2-input NAND functions with open-collector outputs.
NXP 74HC_HCT2G86 Electronic component
The 74HC2G86; 74HCT2G86 is a dual 2-input EXCLUSIVE-OR gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
NXP 74F125 buffer
The 74F125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state.
NXP 74HC_HCT1G00 2-input NAND gate
The 74HC1G00; 74HCT1G00 is a single 2-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
NXP 74AUP1G74 flip-flop
The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for
NXP 74ALVC541 buffer
The 74ALVC541 is an octal non-inverting buffer/line drivers with 3-state bus compatible outputs. The 3-state outputs are controlled by the output enable inputs OE0 and OE1. A HIGH on OEn causes the outputs to assume a high-impedance OFF-state.