Integrated Device Technology Manuals

This datasheet introduces the features of IDT72255 and IDT72265, including storage capacity, read/write clock cycle, retransmit capability, auto power down, master reset, partial reset, empty, full, half-full flag, programmable almost empty and almost full flag, independent read and write clock, select IDT standard timing or first word fall through timing.

This document describes the features and characteristics of IDT7134SA/LA high-speed 4K x 8 dual-port static RAM, including high-speed access, low-power operation, asynchronous operation, battery backup operation, and TTL compatibility.

The IDT71028S70 is a 256K x 4 CMOS static RAM with features including equal access and cycle times (commercial: 70ns), one Chip Select plus one Output Enable pin, bidirectional data Inputs and outputs directly TTL-compatible, low power consumption via chip deselect, and available in 400 mil Plastic SOJ package.

This document describes the features and characteristics of the products IDT54/74FCT373T/2373T and IDT54/74FCT573T/2573T from Integrated Device Technology, Inc. These features include low input and output leakage, CMOS power levels, true TTL input and output compatibility, high drive outputs, power off disable outputs, etc.

The IDT7203/7204/7205/7206 are dual-port memory buffers with internal pointers that load and empty data on a first-in/first-out basis.

IDT72021/031/041s are high-speed, low-power, dual-port memory devices commonly known as FIFOs (First-In/First-Out). Data can be written into and read from the memory at independent rates. The order of information stored and ex- tracted does not change, but the rate of data entering the FIFO might be different than the rate leaving the FIFO. Unlike a Static RAM, no address information is required because the read and write pointers advance sequentially. The IDT72021/ 031/041s can perform asynchronous read and write operations, and have four status flags (Full, Empty, Half-Full and Almost Empty/Almost Full).

IDT71B74 is a high-performance static RAM organized as 8K x 8 and can provide 29 bits of address comparison.

IDT54/74FCT374/534/574 are 8-bit registers with buffered common clock and buffered 3-state output control. When the output enable (OE) is LOW, the eight outputs are enabled. When the OE input is HIGH, the outputs are in the high-impedance state.

IDT7006S/L is a high-speed 16K x 8 dual-port static RAM with true dual-ported memory cells that allow simultaneous reads of the same memory location. It features high-speed access, low-power operation, and the ability to expand data bus width.

The IDT54/74FCT827AT/BT/CT/DT and IDT54/74FCT2827AT/BT/CT are high-performance CMOS buffers for military and commercial temperature ranges. They are built using an advanced dual metal CMOS technology and provide high-performance bus interface buffering for wide data/address paths or buses carrying parity. The buffers have NAND-ed output enables for maximum control flexibility and are designed for high-capacitance load drive capability and low-capacitance bus loading. The FCT2827T has balanced output drive with current limiting resistors, reducing ground bounce, undershoot, and the need for external series terminating resistors.

This document is the datasheet of IDT54/74FCT240/A/C, IDT54/74FCT241/A/C and IDT54/74FCT244/A/C, which introduces the features and characteristics of the products, including functions, pins, packages, speeds, etc.

The IDT7134SA/LA is a high-speed 4K x 8 dual-port static SRAM with features such as high-speed access, low-power operation, fully asynchronous operation from either port, battery backup operation, and TTL compatibility.

This datasheet provides the features and characteristics of IDT54/74FCT16244T/AT/CT/ET, IDT54/74FCT162244T/AT/CT/ET, IDT54/74FCT166244T/AT/CT, IDT54/74FCT162H244T/AT/CT/ET, including interfaces, power consumption, temperature range, etc.