GENNUM Manuals

This data sheet introduces the features and characteristics of the GS4911B/GS4910B HD/SD/Graphics Clock and Timing Generator with GENLOCK product, including video clock synthesis, audio clock synthesis, timing generation and Genlock function.

The GS1531 is a multi-standard serializer from Gennum that supports SMPTE292M, SMPTE259M-C and DVB-ASI standards. It has a 20-bit/10-bit CMOS parallel input data bus, supports 148.5MHz/74.25MHz/27MHz/13.5MHz parallel digital input, and has automatic standard detection and indication functions. It supports 1.8V core power supply and 3.3V charge pump power supply, 3.3V digital I/O power supply, JTAG test interface, and can be used in a lead-free package with a small footprint (11mm x 11mm).

The product is a 3Gb/s, HD, SD SDI receiver with integrated adaptive cable equalizer

The GS4915 is a low jitter clock output chip launched by Gennum. It can reduce jitter for clocks of 148.5MHz, 148.5/1.001MHz, 74.25MHz, 74.25/1.001MHz and 27MHz. The output jitter is as low as 20ps peak to peak, and it can automatically bypass other clock frequencies. In addition, the GS4915 supports single-ended and differential inputs, and has single-ended and differential outputs. It supports LVCMOS and LVDS interfaces and can be widely used in high-definition video systems, digital video recording, playback, processing, and display devices.

This document is a GENNUM GP520A datasheet, which introduces the main features of the product.

The GS9002 is a monolithic bipolar integrated circuit designed to serialize SMPTE 125M and SMPTE 244M bit parallel digital signals as well as other 8 or 10 bit parallel formats. This device performs the functions of sync detection, parallel to serial conversion, data scrambling (using the X9 + X4 +1 algorithm), 10x parallel clock multiplication and conversion of NRZ to NRZI serial data. It supports any of four selectable serial data rates from 100 Mb/s to over 360 Mb/s. The data rates are set by resistors and are selected by an on-board 2:4 decoder having two TTL level input address lines. Other features such as a sync detector output, a sync detector disable input, and a lock detect output are also provided. The X9 + X4 + 1 scrambler and NRZ to NRZI converter may be bypassed to allow the output of the parallel to serial converter to be directly routed to the output drivers. The GS9002 provides pseudo-ECL outputs for the serial data and serial clock as well as a single-ended pseudo-ECL output of the regenerated parallel clock. The GS9002 directly interfaces with cable drivers GS9007, GS9008 and GS9009. The device requires a single +5 volt or -5 volt supply and typically consumes 713 mW of power while driving 100 Ω loads. The 44 pin PLCC packaging assures a small footprint for the complete encoder function.

The GS9090 is a 270Mb/s reclocking deserializer with an internal FIFO. When used in conjunction with one of Gennum’s SDI Cable Equalizers, a receive solution for SD-SDI and DVB-ASI applications can be realized.

GS9025A is a high-performance serial digital signal clock and data recovery chip that supports SMPTE 259M and other data standards, and has automatic cable equalization, automatic rate selection, signal strength indicator output and other functions.