This document is the user guide for PowerPlay Early Power Estimator, which describes the features and characteristics of Stratix, Stratix GX, and Cyclone FPGAs.
This user guide describes how to use PowerPlay Early Power Estimator to estimate the power consumption of designs based on Altera Stratix II, Stratix II GX and HardCopy II devices.
This document describes the PowerPlay Early Power Estimator (PEPE) software, which is a early power estimator for FPGAs. Pepe can estimate the actual running power of FPGA design, and can be used for design evaluation, circuit optimization and cost control.
The IP described in this document is scheduled for product obsolescence and discontinued support. Therefore, Altera does not recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.
This manual introduces the features and usage of the Altera Phase-Locked Loop (ALTPLL) Megafunction. ALTPLL is an important clock generation module in Altera FPGA devices. It can be used to generate stable frequencies, recover signals from a noisy communication channel, or distribute clock signals throughout your design.
This user guide describes the parallel flash loader (PFL) megafunction and provides information about programming flash memory, configuring your FPGA from the flash memory, and instantiating the PFL megafunction in the Quartus® II software. As the density of FPGAs increases, larger configurations need to be configured on the FPGA, and faster configuration speeds are required. The PFL addresses these issues.
