The 74ABT08 high-performance BiCMOS device combines low static and dynamic power
dissipation with high speed and high output drive.
The 74ABT08 is a quad 2-input AND gate.
The 74HC2G86; 74HCT2G86 is a dual 2-input EXCLUSIVE-OR gate. Inputs include
clamp diodes that enable the use of current limiting resistors to interface inputs to voltages
in excess of VCC.
The 74ALVC162835A is an 18-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
When LE is HIGH, the A to Y data flow is transparent. When LE is
LOW and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
The 74ABT2244 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed.
The 74ABT2244 device is an octal buffer that is ideal for driving bus
lines. The device features two Output Enables (1OE, 2OE), each
controlling four of the 3-State outputs.
The 74ABT2244 is designed with 30W series resistance in both the
High and Low states of the output. This design reduces line noise in
applications such as memory address drivers, clock drivers and bus
recei
The 74ALVC162836A is an 20-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
When LE is HIGH, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
The 74ALVC162836A is designed with 30 _series resistors in both
HIGH or LOW output stages.
The 74ABT240 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT240 device is an octal inverting buffer that is ideal for
driving bus lines. The device features two Output Enables (1OE,
2OE), each controlling four of the 3-State outputs.
The 74ABT245 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT245 device is an octal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
The control function implementation minimizes external timing
requirements. The device features an Output Enable (OE) input for
easy cascading and a Direction (DIR) input for direction control.
The 74ABT16823A 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
The 74ABT16823A has two 9-bit wide buffered registers with Clock
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
interfacing in high microprogrammed systems.
The 74ALVC162834A is an 18-bit registered driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
The 74ALVC162834A is designed with 30 _series resistors in both
HIGH or LOW output stages.
The 74ABT16827A high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16827A 20-bit buffers provide high performance bus
interface buffering for wide data/address paths or buses carrying
parity. They have NOR Output Enables (nOE1, nOE2) for maximum
control flexibility
The 74ALVC16836A is a 20-bit universal bus driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
The 74ALVC16834A is an 18-bit registered driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
The 74ABT16374B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16374B has two 8-bit, edge triggered registers, with each
register coupled to eight 3-State output buffers. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
The 74ABT162245A high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed.
The 74ABT162245A device is a 16-bit transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. The control function implementation minimizes
external timing requirements. The device features two Output
Enable (1OE, 2OE) inputs for easy cascading and two Direction
(1DIR, 2DIR) inputs for direction control.
The 74ABT16373B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16373B device is a dual octal transparent latch coupled
to two sets of eight 3-State output buffers. The two sections of the
device are controlled independently by Enable (nE) and Output
Enable (nOE) control gates.
