The LTC2249 is a 14-bit 80Msps, low power 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding imaging and communications applications with AC performance that includes 73dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency.
The LTC2283 is a dual channel 12-bit 125Msps low power 3V ADC designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding imaging and communications applications with AC performance that includes 70.1dB SNR and 82dB SFDR.
The LT1208/LT1209 are dual and quad very high speed operational amplifiers with excellent DC performance. The LT1208/LT1209 feature reduced input offset voltage and higher DC gain than devices with comparable bandwidth and slew rate. Each amplifier is a single gain stage with outstanding settling characteristics. The fast settling time makes the circuit an ideal choice for data acquisition systems. Each output is capable of driving a 500Ω load to ±12V with ±15V supplies and a 150Ω load to ±3V on ±5V supplies. The amplifiers are also capable of driving large capacitive loads which make them useful in buffer or cable driver applications.
The LTC®2356-12/LTC2356-14 are 12-bit/14-bit, 3.5Msps serial ADCs with differential inputs. The devices draw only 5.5mA from a single 3.3V supply and come in a tiny 10-lead MSOP package. A Sleep shutdown feature further reduces power consumption to 13µW. The combination of speed, low power and tiny package makes the LTC2356-12/ LTC2356-14 suitable for high speed, portable applications. The 80dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The devices convert –1.25V to 1.25V bipolar inputs differentially. The absolute voltage swing for AIN+ and AIN– extends from ground to the supply voltage. The serial interface sends out the conversion results during the 16 clock cycles following a CONV rising edge for compatibility with standard serial interfaces. If two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 3.5Msps can be achieved with a 63MHz clock.
