The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type
flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and
complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs
and operate independently of the clock input. Information on the data input is transferred
to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be
stable one set-up time prior to the LOW-to-HIGH clock transition for
The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device
features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume
the state of their corresponding Dn inputs that meet the set-up and hold time requirements
on the LOW-to-HIGH clock (CP) transition. Input E must be stable one set-up time prior to
the LOW-to-HIGH transition for predictable operation. Inputs include clamp diodes that
enable the use of current limiting resistors to interfa
The 74F534 is an 8-bit edge-triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the Clock (CP) and Output Enable (OE) control
gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop
