The 74ALVCH16841 has two 10-bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE) and output enable (nOE)
control gates.
The 74ALVT162821 high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive. It is designed for VCC operation at 2.5V or 3.3V with I/O
compatibility to 5V.
The 74ALVT162821 has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
The 74ALVCH16821 has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
The 74ALVT162245 is a high-performance BiCMOS product
designed for VCC operation at 2.5V or 3.3V with I/O compatibility up
to 5V.
This device is a 16-bit transceiver featuring non-inverting 3-State
bus compatible outputs in both send and receive directions. The
control function implementation minimizes external timing
requirements. The device features an Output Enable (nOE) input for
easy cascading and a Direction (DIR) input for direction control.
The 74ALVT162245 is designed with 30W s
The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring
separate D-type inputs for each flip-flop and 3-state outputs for bus
oriented applications. Incorporates bushold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs. The74ALVCH16823 consists of two sections of nine
edge-triggered flip-flops. A clock (CP) input, an output-enable (OE)
input, a Master reset (MR) input and a clock-enable( CE) input are
provided for each total 9-bit section.
The 74ALVT16373 is a high-performance BiCMOS product
designed for VCC operation at 2.5V or 3.3V with I/O compatibility up
to 5V.
This device is a 16-bit transparent D-type latch with non-inverting
3-State bus compatible outputs. The device can be used as two
8-bit latches or one 16-bit latch. When latch enable (LE) input is
High, the Q outputs follow the data (D) inputs. When latch enable is
taken Low, the Q outputs are latched at the levels of the D inputs
one setup time prior to the Hi
