TEMIC TSC80C31/80C51 handbook
Update: 29 September, 2023
TSC80C31/80C51 is a high-performance SCMOS version of the 8051 NMOS single-chip 8-bit µC. The fully static design of the TSC80C31/80C51 allows for reducing system power consumption by lowering the clock frequency to any value, even DC, without data loss. The TSC80C31/80C51 retains all the features of the 8051: 4K bytes of ROM; 128 bytes of RAM; 32 I/O lines; two 16-bit timers; a 5-source, 2-level interrupt structure; a full-duplex serial port; and on-chip oscillator and clock circuits. Additionally, the TSC80C31/80C51 has two software-selectable modes of reduced activity for further power consumption reduction. In Idle Mode, the CPU is frozen while the RAM, timers, serial port, and interrupt system continue to function. In Power Down Mode, the RAM is saved and all other functions are inoperative. The TSC80C31/80C51 is manufactured using the SCMOS process, allowing them to run from 0 up to 44 MHz with VCC = 5 V. The TSC80C31/80C51 is also available at 20 MHz with 2.7 V < Vcc < 5.5 V.
Brand: TEMIC
File format: PDF
Size: 206 KB
MD5 Checksum: 70657E57392D7419BAC448A8C5CEEB4F
Publication date: 09 May, 2012
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PDF Link: TEMIC TSC80C31/80C51 handbook PDF