Update: 30 September, 2023
CDC2510 is a 3.3V low-skew low-jitter phase-lock loop clock driver designed for synchronous DRAM applications. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CDC2510 operates at 3.3V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. A bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2510 does not require external RC networks. The PLL's loop filter is included on-chip, minimizing power consumption and cost.
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MD5 Checksum: 251D1C1D3DC09952E957E4E90F3A861F
Publication date: 09 May, 2012
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PDF Link: TEXAS INSTRUMENTS CDC2510 DATA SHEET PDF