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- Manuals
- 2
- Last added
- 2012-06-05
Latest HANBit manuals
HANBit HFDOM40S3Rxxx Data Sheet
The HFDOM40S3Rxxx series 40Pin Flash Disk Module is a flash technology based with True IDE interface flash memory card. It is constructed with flash disk controller chip and NAND-type (Samsung) flash memory device. The HFDOM40S3R-xxx series operates in both 3.3-Volt and 5.0-Volt power supplies. It comes in capacity of 16, 32, 48, 64, 80, 96, 128, 144, 160, 192, 208, 224, 256, 272,288, 320, 384 and up to 512MByte formatted 40Pin type . By optimizing flash memory management, the life of this HFDOM40S3Rxxx series can be extended to its maximum level. Because the ECC function is included, the correctness of data transfer between the HFDOM40S3Rxxx series and a True IDE compatible interface device can be guaranteed. The HFDOM40S3Rxxx series is fully compatible with applications such as CPU card / board, set top box, industry / military PC / Notebook, security equipment, measuring instrument and embedded systems.
HANBit HMN1288J Data Sheet
The HMN1288J is a nonvolatile static random access memory produced by HANBit Electronics. It uses a 1,048,576-bit static RAM organization of 131,072 bytes by 8 bits. The product also has an in-built lithium energy source that provides reliable non-volatility, coupled with the unlimited write cycles of standard SRAM and integrated control circuitry that constantly monitors the single 5V supply for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after Vcc returns valid and write protection is unconditionally enabled to prevent garbled data. In addition, the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time, the integral energy source is switched on to sustain the memory until after VCC returns valid. The HMN1288J uses extremely low standby current CMOS SRAMs, coupled with small lithium coin cells to provide non-volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.