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- Manuals
- 2
- Languages
- EN
- Last added
- 2012-05-04
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Analog Devices ADSP-2191 DSP Preliminary Technical Data
The ADSP-2191 is a single‑chip micro‑computing DSP optimized for high‑speed numeric processing. It features a 6.25 ns instruction cycle (160 MIPS), dual‑purpose program memory, a unified 24‑bit address space, and flexible power‑management with programmable PLLs.
The device includes 64 K words of on‑chip SRAM (32 K × 24‑bit program RAM + 32 K × 16‑bit data RAM), three SPORT serial ports, two SPI‑compatible ports, one UART, three programmable 32‑bit timers, up to 11 DMA channels, and is offered in 144‑pin LQFP or 114‑pin BGA packages.
Covers: ADSP‑219x DSP core features · Functional block diagram · Memory architecture · Peripheral architecture · Interrupt controller · DMA controller
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Analog Devices ADSP-2191 DSP Preliminary Technical Data
Datasheet 60 pages · 1.4 MB · ENThe Analog Devices ADSP-2191 DSP preliminary technical data provides architecture, specifications, pinout, and peripheral details for developers.
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Datasheet
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in DSP manuals
What is the instruction cycle time of the ADSP‑2191?
The ADSP‑2191 operates with a 6.25 ns instruction cycle.
From: Analog Devices ADSP-2191 DSP Preliminary Technical Data
How much on‑chip SRAM does the ADSP‑2191 provide?
It provides 64 K words of SRAM, split into 32 K × 24‑bit program RAM and 32 K × 16‑bit data RAM.
From: Analog Devices ADSP-2191 DSP Preliminary Technical Data
