This is a 3-to-8 line decoder/demultiplexer designed for high-performance memory decoding or data routing applications requiring very short propagation delay time. It can be used in high-performance memory systems to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access times of the memory. This means that the effective system delay introduced by the schottky-clamped system decoder is negligible.
