Panasonic Manuals

This is a document about the 2SC1318A silicon NPN epitaxial planar transistor. It is suitable for the driver stage of a low-frequency amplifier, with a high collector to emitter voltage VCEO. It is also optimum for the driver stage of a low-frequency and 25 to 30W output amplifier. The document also provides the absolute maximum ratings and electrical characteristics of the product.

2SC1359 is a NPN type transistor, with high frequency amplification characteristics, suitable for FM/AM radios and other scenes

2SC1360, 2SC1360A is a silicon NPN epitaxial planar type for intermadiate frequency amplification of TV image

2SC1383, 2SC1384 are silicon NPN epitaxial planar type transistors for low-frequency power amplification and driver amplification.

2SD1772, 2SD1772A are silicon NPN triple diffusion planar type power transistors, used for power amplification, used for TV vertical deflection output, complementary to 2SB1192 and 2SB1192A

This document describes the features and characteristics of Composite Transistors XN06211 (XN6211), which is a silicon NPN epitaxial planar transistor for switching/digital circuits. The product incorporates two elements into one package, reducing the mounting area and assembly cost. The document also provides the absolute maximum ratings and electrical characteristics of the product.

LN533YAMY, LN533YKMY, LN533OAMG and LN533OKMG are 7.6mm(.3”) series 3-digit numeric displays with amber and orange lighting colors.

This data sheet lists the UNR111x series' characteristics parameters, including package, absolute maximum ratings, internal connection, etc.

The MN63121 is a 1K-bit EEPROM supporting serial I/O and operating on a single power supply with a volt- age between 1.8 and 5.5 V. It provides the following pins for easy interfacing to microprocessors or microcontrollers: chip select (CS), serial clock (SCK), data input (DI), data output (DO), reset (RESET), and busy (RDY/BUSY). It includes a built-in timer for use in automatically erasing and writing data during data up- date operations. The memory organization is 64 × 16 bits. The chip in- dicates the end of a write operation with either the RDY/ BUSY pin or the state of the DO pin after the status out- put mode has been set. Conversion of peripheral circuits to CMOS realizes great reductions in power consumption. Use of floating gate memory cells and a built-in error correction circuit ensures reliable operation for 105 write cycles.

MVCA1Z, MVCA2Z SD Card Host IP is a hardware IP that implements the CPRM (Content Protection for Recordable Media*) function with an SD host device.

This document is the datasheet for Panasonic PUB4118(PU4118), including pin definition, package form, maximum ratings, characteristic curves, application circuits, etc.