P89C60X2/61X2 devices adopt a high-performance static 80C51 design, manufactured using advanced CMOS process and include non-volatile Flash program memory. Can be programmed by parallel programming or in-system programming (ISP). Support 6 clock and 12 clock modes. P89C60X2 and P89C61X2 include 512 bytes and 1024 bytes of RAM, 32 I/O ports, 3 16-bit timers/counters, 6 interrupt sources-4 interrupt priorities-nested interrupt structures, 1 enhanced UART, watchdog timer and on-chip oscillator and clock circuits. In addition, the static design of the device provides a very wide frequency range, even as low as zero. It has two software-selectable power-saving modes, idle mode and power-down mode. The idle mode freezes the operation of the CPU but allows RAM, timers, serial ports and interrupt systems to continue to maintain their functionality. The power-down mode keeps the RAM contents, but freezes the oscillator, thus stopping all other on-chip functions. Since it is a static design, the clock stops without losing user data. Operation can be restored from the clock stop point.
