ST 74LVC373A handbook
Update: 30 September, 2023
The 74LVC373A is a low voltage CMOS 8-bit D-type latch fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs are equipped with protection circuits
Brand: ST
File format: PDF
Size: 76 KB
MD5 Checksum: F9530DDBEF78E3EAFC5CE3C95B3C9F92
Publication date: 03 May, 2012
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PDF Link: ST 74LVC373A handbook PDF